1. Technical Field
The present invention relates to a semiconductor memory apparatus and a semiconductor system including the same.
2. Related Art
A semiconductor memory apparatus includes a plurality of pads (or pins) and communicates with an external controller through the plurality of pads. While the pads are essential component elements of the semiconductor memory apparatus for communicating with the external controller, the presence of the pads may adversely influence the miniaturization of the semiconductor memory apparatus. That is to say, as a semiconductor memory apparatus has large capacity, the number of pads increases, and the area occupied by the pads correspondingly increases.
FIG. 1 is a diagram schematically illustrating the configuration of a known semiconductor memory apparatus. FIG. 1 shows four pads which are used in the data input/output operations, that is, read and write operations, of a semiconductor memory apparatus. The four pads are a data pad 10, a read data strobe pad 20, a write data strobe pad 30, and a data mask pad 40.
The data pad 10 is provided to input data DQ<0:31> to the semiconductor memory apparatus or output data DQ<0:31> from the semiconductor memory apparatus.
The read data strobe pad 20 is a pad for outputting a read data strobe signal RDQS<0:3> outputted with the read data, to be used in capturing the read data at a receiver, e.g., an external controller.
The write data strobe pad 30 is a pad for receiving a write data strobe signal WDQS<0:3> received with the write data, to be used in capturing the write data at the semiconductor memory apparatus
The data mask pad 40 is a pad for receiving a data mask signal DM<0:3>. The data mask signal DM<0:3> is used in the write operation of the semiconductor memory apparatus. The data mask signal DM<0:3> functions to prevent data, currently inputted to the semiconductor memory apparatus through the data pad 10, from being transferred to an internal circuit of the semiconductor memory apparatus, when a change of the data stored in the semiconductor memory apparatus is not required depending upon a data pattern.
FIG. 2 is a timing diagram illustrating the operations of the known semiconductor memory apparatus. The operations of the known semiconductor memory apparatus will be described below with reference to FIGS. 1 and 2. In FIG. 2, a write command WT is inputted for the write operation of the semiconductor memory apparatus. If the write command WT is inputted, the semiconductor memory apparatus receives input data DQ<0:31> through the data pad 10, the write data strobe signal WDQS<0:3> through the write data strobe pad 30, and the data mask signal DM<0:3> through the data mask pad 40. In FIG. 2, if the data mask signal DM<0:3> is enabled, currently inputted data is masked, and if the data mask signal DM is disabled, the currently inputted data is not masked.
Thereafter, when performing the read operation, a read command RD is applied to the semiconductor memory apparatus. If the read command RD is applied, output data DQ<0:31> is outputted to the external controller through the data pad 10, and the read data strobe signal RDQS<0:3> is outputted to the external controller through the read data strobe pad 20.